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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 0 1 publication order number: cat9534/d cat9534 8-bit i 2 c and smbus i/o port with interrupt description the cat9534 is an 8 ? bit parallel input/output port expander for i 2 c and smbus compatible applications. these i/o expanders provide a simple solution in applications where additional i/os are needed: sensors, power switches, leds, pushbuttons, and fans. the cat9534 consists of an input port register, an output port register, a configuration register, a polarity inversion register and an i 2 c/smbus ? compatible serial interface. any of the eight i/os can be configured as an input or output by writing to the configuration register. the system master can invert the cat9534 input data by writing to the active ? high polarity inversion register. the cat9534 features an active low interrupt output which indicates to the system master that an input state has changed. the device?s extended addressing capability allows up to 8 devices to share the same bus. cat9534 is offered in 16 pin soic, tssop and tqfn packages and operates over the full ? 40 c to +85 c industrial temperature range. features ? 400 khz i 2 c bus compatible ? 2.3 v to 5.5 v operation ? low stand ? by current ? 5 v tolerant i/os ? 8 i/o pins that default to inputs at power ? up ? high drive capability ? individual i/o configuration ? polarity inversion register ? active low interrupt output ? internal power ? on reset ? no glitch on power ? up ? noise filter on sda/scl inputs ? cascadable up to 8 devices ? industrial temperature range ? 16 ? lead soic and tssop, and 16 ? pad tqfn (4 x 4 mm) packages ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? white goods (dishwashers, washing machines) ? handheld devices (cell phones, pdas, digital cameras) ? data communications (routers, hubs and servers) tqfn ? 16 hv4 suffix case 510ae http://onsemi.com soic ? 16 w suffix case 751bg pin connections soic (w), tssop (y) (top view) 1 a0 a1 a2 i/o 1 i/o 0 v cc sda scl int i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 3 v ss tssop ? 16 y suffix case 948an see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information tqfn 4 x 4 mm (hv4) (top view) scl int i/o 7 i/o 6 a2 i/o 1 i/o 0 i/o 2 a1 a0 v cc sda i/o 3 i/o 4 v ss i/o 5 1
cat9534 http://onsemi.com 2 figure 1. block diagram 8 ? bit write pulse read pulse lp filter power ? on reset input filter control a0 a1 a2 sda scl input/ output ports int v cc i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i 2 c/smbus v cc v ss note: all i/os are set to inputs at reset. table 1. pin description soic / tssop tqfn pin name function 1 15 a0 address input 0 2 16 a1 address input 1 3 1 a2 address input 2 4 ? 7 2 ? 5 i/o 0 ? 3 input/output port 0 to input/output port 3 8 6 v ss ground 9 ? 12 7 ? 10 i/o 4 ? 7 input/output port 4 to input/output port 7 13 11 int interrupt output (open drain) 14 12 scl serial clock 15 13 sda serial data 16 14 v cc power supply table 2. absolute maximum ratings parameters ratings units v cc with respect to ground ? 0.5 to +6.5 v voltage on any pin with respect to ground ? 0.5 to +5.5 v dc current on i/o 0 to i/o 7 50 ma dc input current 20 ma v cc supply current 85 ma v ss supply current 100 ma package power dissipation capability (t a = 25 c) 1.0 w junction temperature +150 c storage temperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. reliability characteristics symbol parameter reference test method min units v zap (note 1) esd susceptibility jedec standard jesd 22 2000 volts i lth (notes 1, 2) latch ? up jedec standard 17 100 ma 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch ? up protection is provided for stresses up to 100 ma on address and data pins from ? 1 v to v cc +1 v.
cat9534 http://onsemi.com 3 table 4. d.c. operating characteristics (v cc = 2.3 to 5.5 v; t a = ? 40 c to +85 c, unless otherwise specified.) symbol parameter conditions min typ max unit supplies v cc supply voltage 2.3 ? 5.5 v i cc supply current operating mode; v cc = 5.5 v; no load; f scl = 100 khz ? 104 175 a i stbl standby current standby mode; v cc = 5.5 v; no load; v i = v ss ; f scl = 0 khz; i/o = inputs ? 0.25 3 a i stbh standby current standby mode; v cc = 5.5 v; no load; v i = v cc ; f scl = 0 khz; i/o = inputs ? 0.25 1 a v por power ? on reset voltage no load; v i = v cc or v ss ? 1.5 1.65 v scl, sda, int v il (note 3) low level input voltage ? 0.5 ? 0.3 x v cc v v ih (note 3) high level input voltage 0.7 x v cc ? 5.5 v i ol low level output current v ol = 0.4 v 3 ? ? ma i l leakage current v i = v cc or v ss ? 1 ? +1 a c i (note 4) input capacitance v i = v ss ? ? 6 pf c o (note 4) output capacitance v o = v ss ? ? 8 pf a0, a1, a2 v il (note 3) low level input voltage ? 0.5 ? 0.8 v v ih (note 3) high level input voltage 2.0 ? 5.5 v i li input leakage current ? 1 ? 1 a i/os v il low level input voltage ? 0.5 ? 0.8 v v ih high level input voltage 2.0 ? 5.5 v i ol low level output current v ol = 0.5 v; v cc = 2.3 v (note 5) 8 10 ? ma v ol = 0.7 v; v cc = 2.3 v (note 5) 10 13 ? ma v ol = 0.5 v; v cc = 4.5 v (note 5) 8 17 ? ma v ol = 0.7 v; v cc = 4.5 v (note 5) 10 24 ? ma v ol = 0.5 v; v cc = 3.0 v (note 5) 8 14 ? ma v ol = 0.7 v; v cc = 3.0 v (note 5) 10 19 ? ma v oh high level output voltage i oh = ? 8 ma; v cc = 2.3 v (note 6) 1.8 ? ? v i oh = ? 10 ma; v cc = 2.3 v (note 6) 1.7 ? ? v i oh = ? 8 ma; v cc = 3.0 v (note 6) 2.6 ? ? v i oh = ? 10 ma; v cc = 3.0 v (note 6) 2.5 ? ? v i oh = ? 8 ma; v cc = 4.75 v (note 6) 4.1 ? ? v i oh = ? 10 ma; v cc = 4.75 v (note 6) 4.0 ? ? v i l input leakage current v cc = 3.6 v; v i = v cc ? ? 1 a c i (note 4) input capacitance ? ? 5 pf c o (note 4) output capacitance ? ? 8 pf 3. v il min and v ih max are reference values only and are not tested. 4. this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. 5. the total current sunk by all i/os must be limited to 100 ma and each i/o limited to 25 ma maximum. 6. the total current sourced by all i/os must be limited to 85 ma.
cat9534 http://onsemi.com 4 table 5. a.c. characteristics (v cc = 2.3 to 5.5 v; t a = ? 40 c to +85 c, unless otherwise specified.) (note 7) symbol parameter standard i 2 c fast i 2 c units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r (note 8) sda and scl rise time 1000 300 ns t f (note 8) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf (note 8) bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 50 ns t i (note 8) noise pulse filtered at scl and sda inputs 100 100 ns symbol parameter min max units port timing t pv output data valid 200 ns t ps input data setup time 100 ns t ph input data hold time 1 s interrupt timing t iv interrupt valid 4 s t ir interrupt reset 4 s 7. test conditions according to ?ac test conditions? table. 8. this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. table 6. a.c. test conditions input rise and fall time 10 ns cmos input voltages 0.2 v cc to 0.8 v cc cmos input reference voltages 0.3 v cc to 0.7 v cc ttl input voltages 0.4 v to 2.4 v ttl input reference voltages 0.8 v, 2.0 v output reference voltages 0.5 v cc output load: sda, int current source i ol = 3 ma; c l = 100 pf output load: i/os current source: i ol /i oh = 10 ma; c l = 50 pf
cat9534 http://onsemi.com 5 scl sda in sda out figure 2. i 2 c serial interface timing t su:sta t aa t f t hd:sta t hd:dat t low t dh t r t su:dat t low t high t su:sto t buf pin description scl: serial clock the serial clock input clocks all data transferred into or out of the device. the scl line requires a pull ? up resistor if it is driven by an open drain output. sda: serial data/address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire ? ored with other open drain or open collector outputs. a pull ? up resistor must be connected from sda line to v cc . the value of the pull ? up resistor, r p , can be calculated based on minimum and maximum values from figure 3 and figure 4 (see note). a0, a1, a2: device address inputs these inputs are used for extended addressing capability. the a0, a1, a2 pins should be hardwired to v cc or v ss . when hardwired, up to eight cat9534s may be addressed on a single bus system. the levels on these inputs are compared with corresponding bits, a2, a1, a0, from the slave address byte. i/o 0 to i/o 7 : input / output ports any of these pins may be configured as input or output. the simplified schematic of i/o 0 to i/o 7 is shown in figure 5. when an i/o is configured as an input, the q1 and q2 output transistors are off creating a high impedance input. if the i/o pin is configured as an output, the push ? pull output stage is enabled. care should be taken if an external voltage is applied to an i/o pin configured as an output due to the low impedance paths that exist between the pin and either v cc or v ss . figure 3. minimum r p value vs. supply voltage figure 4. maximum r p value vs. bus capacitance v cc (v) c bus (pf) 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 0 0.5 1.0 1.5 2.0 2.5 400 350 300 200 150 100 50 0 0 1 2 3 4 6 7 8 r pmin (k ) r pmax (k ) 5.2 5.6 i ol = 3 ma @ v olmax 250 5 fast mode i 2 c bus / tr max ? 300 ns note: according to the fast mode i 2 c bus specification, for bus capacitance up to 200 pf, the pull up device can be a resistor. for bus loads between 200 pf and 400 pf, the pull ? up device can be a current source (imax = 3 ma) or a switched resistor circuit.
cat9534 http://onsemi.com 6 int : interrupt output the open ? drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). the interrupt is deactivated when the input returns to its previous state or the input port register is read. changing an i/o from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. output port register data input port register data polarity register data polarity inversion register write polarity register data from shift register read pulse write pulse write configuration data from shift register data from shift register configuration register d q ff d q ff d q latch d q ff q1 q2 output port register input port register figure 5. simplified schematic of i/o 0 to i/o 7 pulse q c k q c k c k q q c k to int v ss v cc i/o 0 to i/o 7
cat9534 http://onsemi.com 7 functional description cat9534?s general purpose input/ output (gpio) peripherals provide up to eight i/o ports, controlled through an i 2 c compatible serial interface. the cat9534 supports the i 2 c bus data transmission protocol. this i 2 c bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the ca t9534 operates as a slave device. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition (figure 6). start and stop conditions the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat9534 monitors the sda and scl lines and will not respond until this condition is met. a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing after the bus master sends a start condition, a slave address byte is required to enable the cat9534 for a read or write operation. the four most significant bits of the slave address are fixed as binary 0100 and the next three bits are its individual address bits (figure 7). the address bits a2, a1 and a0 are used to select which device is accessed from maximum eight devices on the same bus. these bits must compare to their hardwired input pins. the 8th bit following the 7 ? bit slave address is the r/w bit that specifies whether a read or write operation is to be performed. when this bit is set to ?1?, a read operation is initiated, and when set to ?0?, a write operation is selected. following the start condition and the slave address byte, the cat9534 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat9534 then performs a read or a write operation depending on the state of the r/w bit. start condition stop condition sda scl figure 6. start/stop condition 0 1 0 0 a2 a1 a0 slave address fixed programmable hardware selectable figure 7. cat9534 slave address r/w
cat9534 http://onsemi.com 8 acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the sda line remains stable low during the high period of the acknowledge related clock pulse (figure 6). the cat9534 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 ? bit byte. when the cat9534 begins a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat9534 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. the master must then issue a stop condition to return the cat9534 to the standby power mode and place the device in a known state. registers and bus transactions the cat9534 consists of an input port register, an output port register, a polarity inversion register and a configuration register. table 7 shows the register address table. tables 8 to 11 list register 0 through register 3 information. table 7. register command byte command (hex) protocol function 0x00 read byte input port register 0x01 read/write byte output port register 0x02 read/write byte polarity inversion register 0x03 read/write byte configuration register the command byte is the first byte to follow the device address byte during a write/read bus transaction. the register command byte acts as a pointer to determine which register will be written or read. the input port register is a read only port. it reflects the incoming logic levels of the i/o pins, regardless of whether the pin is defined as an input or an output by the configuration register. writes to the input port register are ignored. table 8. register 0 ? input port register bit i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 default 1 1 1 1 1 1 1 1 table 9. register 1 ? output port register bit o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 default 1 1 1 1 1 1 1 1 table 10. register 2 ? polarity inversion register bit n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 default 0 0 0 0 0 0 0 0 table 11. register 3 ? configuration register bit c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 default 1 1 1 1 1 1 1 1 figure 8. acknowledge timing 189 start scl from master bus release delay (transmitter) ack delay ack setup bus release delay (receiver) data output from transmitter data output from receiver
cat9534 http://onsemi.com 9 the output port register sets the outgoing logic levels of the i/o ports, defined as outputs by the configuration register. bit values in this register have no effect on i/o pins defined as inputs. reads from the output port register reflect the value that is in the flip ? flop controlling the output, not the actual i/o pin value. the polarity inversion register allows the user to invert the polarity of the input port register data. if a bit in this register is set (?1?) the corresponding input port data is inverted. if a bit in the polarity inversion register is cleared (?0?), the original input port polarity is retained. the configuration register sets the directions of the ports. set the bit in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. if a bit in this register is cleared, the corresponding port pin is enabled as an output. at power ? up, the i/os are configured as inputs with a weak pull ? up resistor to v cc . data is transmitted to the cat9534?s registers using the write mode shown in figure 9 and figure 10. the cat9534? s registers are read according to the timing diagrams shown in figure 11 and figure 12. once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte will be sent. 12345678 9 scl sda write to port data out from port s0100a2 a00 a a1 00000 001 a data 1 a p acknowledge from slave acknowledge from slave acknowledge from slave slave address command byte data to port start condition stop condition data 1 valid figure 9. write to output port register 12345678 9 scl sda write to register s0100a2 a00 a a1 00000 011/0 data 1 a a p acknowledge from slave acknowledge from slave acknowledge from slave slave address command byte data to register start condition stop condition figure 10. write to configuration or polarity inversion register r/w r/w t pv
cat9534 http://onsemi.com 10 interrupt output cat9534?s interrupt otuput is an active low open ? drain output that is activated when any port pin configured as an input changes state. the interrupt output is reset when the input returns to its previous state or the input port register is read. note that changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. power ? on reset operation when the power supply is applied to v cc pin, an internal power ? on reset pulse holds the ca t9534 in a reset state until v cc reaches v por level. at this point, the reset condition is released and the internal state machine and the cat9534?s registers are initialized to their default state. 12345678 9 scl sda read from port data into port s0100a2 a01 a a1 a data 4 na p no acknowledge from master acknowledge from master acknowledge from slave slave address data from port start condition stop condition data 2 data 3 data 4 data 1 data from port data 1 data s0100a2 a00 a a1 0 1 0 0 a2 a1 a0 a data a acknowledge from master acknowledge from slave slave address slave address data from register command byte as 1 acknowledge from slave acknowledge from slave at this moment master ? transmitter becomes master ? receiver and slave ? receiver becomes slave ? transmitter na no acknowledge from master data from register p last byte first byte figure 11. read from register figure 12. read input port register t ir t iv int t ph r/w t ps r/w r/w
cat9534 http://onsemi.com 11 package dimensions soic ? 16, 150 mils case 751bg ? 01 issue o top view pin#1 identification e d a e b a1 l h c e1 side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 9.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 10.00 6.20 4.00 l 0.40 1.27 1.35 9.90 6.00 3.90
cat9534 http://onsemi.com 12 package dimensions tqfn16, 4x4 case 510ae ? 01 issue a e2 a3 e b l a a1 side view top view bottom view e d pin#1 index area pin#1 id detail a detail a front view a1 a d2 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-220. symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.25 0.30 0.35 d 3.90 4.00 4.10 d2 2.00 ??? 2.25 e 4.00 e2 2.00 ??? 2.25 e 3.90 0.65 bsc 4.10 l 0.45 ??? 0.65
cat9534 http://onsemi.com 13 package dimensions tssop16, 4.4x5 case 948an ? 01 issue o pin#1 identification 1 a1 a2 d top view side view end view e e1 b l1 c l a symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.85 0.19 0.13 0.45 4.90 6.30 4.30 0.65 bsc 1.00 ref 1.10 0.15 0.95 0.30 0.20 0.75 5.10 6.50 4.50 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. e
cat9534 http://onsemi.com 14 example of ordering information (note 11) prefix device # suffix company id cat 9534 product number 9534 t2 t: tape & reel 2: 2,000 / reel tape & reel (note 13) (optional) w package ? g g: nipdau blank: matte ? tin lead finish w: soic y: tssop hv4: tqfn temperature range i = industrial ( ? 40 c to +85 c) i table 12. ordering information part number package lead finish cat9534wi ? gt2 soic nipdau cat9534yi ? gt2 tssop nipdau cat9534hv4i ? gt2 tqfn nipdau 9. all packages are rohs ? compliant (lead ? free, halogen ? free). 10. the standard lead finish is nipdau. 11. the device used in the above example is a cat9534wi ? gt2 (soic, industrial temperature, nipdau, tape & reel, 2,000/reel). 12. for additional package and temperature options, please contact your nearest on semiconductor sales office. 13. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat9534/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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